The present invention relates to a system and process for surface passivation of a semiconductor substrate surface. More particularly the present invention relates to a system and process for surface passivation, which produces a passivated semiconductor substrate surface that allows for effective characterization of the electrical properties of the semiconductor substrate layer underlying the passivated substrate surface.
Regardless of the cleanliness of the semiconductor wafer processing environment, some electrically active contaminants end up in or on the semiconductor wafer surface. In order to protect the wafer or its surface from such contaminants, the top layer of the wafer surface, which typically includes silicon, is oxidized to serve as a protective coating. During the wafer surface oxidation or passivation process, as it is commonly known, the top layer of silicon is converted to silicon oxide or some other semiconductor oxide.
FIG. 1 shows a portion of a semiconductor wafer 10 having a bulk silicon layer 14, above which is disposed a silicon dioxide (SiO2) layer 12 (hereinafter interchangeably referred to as the xe2x80x9coxide layerxe2x80x9d or xe2x80x9cpassivated surfacexe2x80x9d) that may be fabricated by surface passivation techniques described below. In the presence of such a passivated surface, contaminants landing on the wafer surface end up on the new oxide layer 12 away from the electrically active semiconductor layer or the bulk silicon layer 14. However, contaminants disposed above the oxide layer impede the electrical characterization of bulk silicon layer 14 underlying the passivated wafer surface (hereinafter referred to as the xe2x80x9cunderlying layer 14xe2x80x9d to facilitate discussion). The electrical characterization, e.g., resistivity being most common, of underlying layer 14 is an important specification desired by a purchaser or consumer of semiconductor wafers and/or chips because, among other factors, the electrical properties of underlying layer 14 significantly impact the electrical performance of the active devices formed in the underlying layer.
The wafer surface passivation process, i.e. fabrication of oxide layer 12 of FIG. 1, is currently accomplished either through wet chemistry or by thermal oxidation. According to the wet chemistry method, the wafer surface, which is typically includes silicon, is exposed at low temperatures, e.g., about 80xc2x0 C., to an aqueous oxidizing solution that oxidizes or passivates the wafer surface and forms silicon dioxide (SiO2) thereon. There are oxidizing solutions of different compositions that are commercially available to accomplish wafer surface oxidation. Some compositions of the commercially available oxidizing solution are proprietary. Other compositions of the oxidizing solution, however, are well known. A representative aqueous oxidizing solution composition includes hydrogen peroxide, hydrogen fluoride, ammonium fluoride, etc. Another representative aqueous oxidizing solution composition includes ozone and hydrogen fluoride. After the wafer surface is oxidized using wet chemistry, it undergoes drying which requires a drying apparatus and additional equipment associated with such an apparatus.
Although the wet chemistry method passivates the wafer surface at the desired relatively low temperatures, it suffers from several drawbacks. By way of example, the wet chemistry surface method produces an oxide layer of poor quality that does not allow for simple and reproducible measurements of the electrical properties of the underlying layer. Consequently, it is difficult to ensure a purchaser or consumer of semiconductor wafer and/or chips that the electrical properties of the underlying layer meets their specifications, without utilizing destructive measurement techniques.
As another example, after the wafers are exposed to a wet chemistry solution, they are dried using a drying apparatus, which requires added cost and space for additional equipment. The wet chemical passivation and drying steps are also time consuming and, therefore, lower the throughput of the wafer surface passivation process. The problems associated with limited cost and space are further aggravated when additional resources are expended for environmentally safe disposal of the wet chemistry solutions.
As yet another example, the wet chemistry approach described above may also introduce contaminants from the oxidizing solution on the wafer surface. These contaminants include dissolved metals or particles and may also exacerbate the problem of measuring the electrical properties of the underlying layer.
Thermal oxidation is another method that is traditionally employed to accomplish surface passivation. Those skilled in the art recognize that thermal oxidation offers many advantages associated with dry processing, i.e. processing in the absence of an aqueous oxidizing solution, that are not realized by the wet chemistry method. A few advantages of dry processing by thermal oxidation include eliminating contamination caused by the aqueous oxidizing solution and the need for a drying apparatus and other equipment used in conjunction with the drying apparatus.
Thermal oxidation typically begins when a wafer is loaded into a tube furnace containing an oxidizing environment and the temperature inside the furnace is raised to relatively high temperatures, e.g., 900xc2x0 C. and higher. An oxidizing environment may contain oxygen or ozone in various concentrations. Any ozone gas used in the tube furnace is produced ex-situ, i.e. outside the tube furnace, and is transported inside the tube furnace through appropriate equipment, such as pipes, valves and the like, during thermal oxidation. In order to accomplish the required extent of passivation, the wafer is exposed to such high temperatures for about 2 hours or more. The heated wafer surface is cooled before the electrical properties of the underlying layer are determined.
Another thermal oxidation technique involves oxidizing the wafer at temperatures of about 1000xc2x0 C. and higher in a Rapid Thermal Oxidation (RTO) apparatus for a short period of time, e.g., 30 seconds. In order to make the electrical properties of the underlying layer measurable, the oxidized wafer surface is subjected to Rapid Thermal Annealing (RTA) in a nitrogen and/or argon gas environment maintained at the same relatively high temperatures as the oxidation process.
Unfortunately, the thermal oxidation techniques discussed above also suffer from several drawbacks. By way of example, the dopant concentration profile, the oxygen precipitation level and mechanical properties of the wafer are not preserved due to the high thermal budget of the thermal oxidation process. FIG. 2 shows a portion of a epitaxial silicon wafer 20 having a passivated surface and the layer stack of this wafer is discussed hereinafter as an example to facilitate discussion regarding the undesirable effects of high temperature treatments on a wafer during thermal oxidation.
Epitaxial silicon wafer 20 includes an epitaxial silicon layer 24 fabricated above a bulk silicon layer 26. Those skilled in the art will recognize that epitaxial silicon layer has a greater degree of silicon purity than bulk silicon layer 26, which may be more conductive due to a higher dopant concentration than epitaxial layer 24. Furthermore, the high purity of the epitaxial layer makes it suitable for many applications and is generally a desired feature by purchasers or consumers of semiconductor wafers and/or chips. An oxide layer 22, as shown in FIG. 2, is fabricated above epitaxial layer 24 to reduce the reactivity of the surface of epitaxial silicon wafer 20.
FIG. 3 shows a graph of resistivity, which is shown on vertical axis 32, versus the depth of the epitaxial silicon wafer from the top of the epitaxial layer, which depth is shown on horizontal axis 34. It is well known to those skilled in the art that the resistivity of a layer is inversely proportional to the dopant concentration in that layer and, therefore, the resistivity of epitaxial silicon layer 24 is higher than that of silicon bulk layer 26 of FIG. 2. For these reasons, the terms xe2x80x9cresistivity profilexe2x80x9d and xe2x80x9cdopant concentration profilexe2x80x9d convey the same idea in the discussion set forth below and the term xe2x80x9cdopant concentration profilexe2x80x9d is used instead of the term xe2x80x9cresistivity profilexe2x80x9d hereinafter. Thus, also shown in FIG. 3 are dopant concentration profiles 36 and 38 that extend across the epitaxial silicon layer, a transition width region 40 and bulk silicon layer of an epitaxial silicon wafer. Dopant concentration profile 38 represents the dopant concentration profile in an epitaxial silicon wafer after the epitaxial silicon wafer is fabricated, but before the wafer is subjected to thermal oxidation. Dopant concentration profile 36 represents the resulting dopant concentration profile of an epitaxial silicon wafer after its surface has been subjected to thermal oxidation. Transition width 40 represents a region of transition between the epitaxial silicon layer and bulk silicon layer.
The shape of the dopant concentration profile in the transition width, such as the shape of dopant concentration profile 38 of FIG. 3, is usually specified by the purchaser or consumer of semiconductor wafers and/or chips. In transition width region 40, dopant concentration profile 38 shows a steep drop in resistivity and delineates between a silicon layer of high purity and relatively low dopant concentration and a bulk silicon layer with high dopant concentration in the transition width region. During surface passivation, however, there is a need to preserve dopant concentration profile 38 and thereby ensure that high silicon purity of the epitaxial layer will be maintained and the epitaxial layer will serve as intended.
In this context, however, dopant concentration profile 36 is undesired because it indicates excessive diffusion of the dopant atoms from the bulk silicon layer to the epitaxial silicon layer and across the transition width. The excessive diffusion of dopant atoms alters the characteristics, electrical properties in particular, of the epitaxial silicon layer. High temperature treatment encountered by the wafer during thermal oxidation cause such excessive diffusion of the dopant atoms. Consequently, there is no clear delineation between the epitaxial silicon layer and the bulk silicon layer. Dopant concentration profile 36 illustrates that high temperature treatments performed during thermal oxidation defeat the purpose of expending significant time and resources to fabricate a silicon layer of high purity and render thermal oxidation an unattractive method for surface passivation.
Regarding oxygen precipitation level, it should be borne in mind that a certain amount of oxygen precipitation is desired because it facilitates in gettering metallic impurities, for example. A purchaser or consumer of semiconductor wafers and/or chips typically specifies the desired amount of oxygen precipitation and the epitaxial silicon wafer is fabricated to have this specified or appropriate oxygen precipitation level. High temperature treatments during thermal oxidation, however, undesirably alter the oxygen precipitation level. Specifically, high temperatures induce excessive oxygen precipitation causing sufficient amounts of oxygen atoms to diffuse and precipitate out as crystal silicon dioxide.
Those skilled in the art will recognize that exposure of the wafer surface to high temperatures during thermal oxidation undesirably alters the mechanical properties of the wafer. In particular, wafer mechanical properties such as wafer flatness, warping and bowing, which are typically specified by purchasers or consumers of semiconductor wafers and/or chips, are altered due to high temperature treatments. It is well known that changes in such mechanical properties can detrimentally impact the wafer resulting after subsequent wafer fabrication steps, such as photolithography, and thereby lower die yield.
What is, therefore, needed is a system and method for surface passivation that allows for fast and reproducible measurements of the electrical properties of the underlying layer by employing non-destructive techniques, without suffering from the drawbacks associated with wet chemistry and thermal oxidation.
The present invention provides a system and method for surface passivation that allows for fast and reproducible measurements of the electrical properties of the underlying layer. The present invention enjoys the advantages offered by wet chemistry (e.g., of low temperature processing) and thermal oxidation (e.g., of producing a high quality oxide layer by employing a simple design for dry processing), without suffering from the drawbacks associated with wet chemistry and thermal oxidation.
It should be borne in mind that after a semiconductor substrate, e.g., a silicone wafer, a silicone germanium wafer or those wafers having an epitaxial surface layer, is fabricated and before the substrate surface is oxidized, the electrical properties of the substrate layer underlying the passivated surface (hereinafter referred to as xe2x80x9cunderlying substrate layerxe2x80x9d to facilitate discussion) are not always measurable. Whether the electrical properties of the underlying substrate layer are measurable or not they depend on how long the substrate has been out of the reactor and exposed to the environment after the substrate was fabricated. In those instances when the electrical properties of the underlying substrate layer are measurable, it has been found that such measurements are not reproducible over time. Consequently, it is difficult for the semiconductor fabrication facility to know with any degree of certainty whether the properties of the semiconductor substrate need a customer specifications. To this end, the present invention provides a surface passivation process that guarantees reproducible measurements of the underlying substrate layer, which measurements are independent of time, i.e. the period of time that the substrate surface is exposed to the environment after fabrication and before passivation.
The present invention, in accordance with one embodiment, provides a process for effectively reducing reactivity of a surface of a semiconductor substrate. The process includes: (1) oxidizing in an oxidizing environment the surface of a semiconductor misubstrate, which has a dopant concentration profile that extends across a depth of the semiconductor substrate; and (2) annealing the semiconductor substrate surface in an inert gas environment, wherein oxidizing and annealing of the semiconductor substrate surface are performed at relatively low temperatures. In one embodiment of the present invention, the temperatures of oxidizing and annealing, which may be the same, are sufficiently low to substantially preserve the dopant concentration profile in the semiconductor substrate. In another embodiment of the present invention, the temperatures are sufficiently low to substantially preserve the oxygen precipitation level of the semiconductor substrate. In yet another embodiment, the temperatures are sufficiently low to substantially preserve the mechanical properties of the substrate.
It is noteworthy that due to the drawbacks of wet chemistry and thermal oxidation, 1 or 2 semiconductor substrates serve as test substrates for a substrate production lot and the electrical properties of the underlying substrate layers of the test substrates are considered to be representative of the substrate production lot. A substrate production lot refers to a collection of about 25 semiconductor substrates that are processed together under substantially similar processing conditions. If substrate surface passivation is performed using thermal oxidation, then generally only the test substrates undergo the high thermal cycling described above and the remaining substrates of the production lot may be passivated without being subjected to the same high temperatures. Thus, alterations in the dopant concentration profile, oxygen precipitation level and mechanical properties of the test substrate, as described above, make the properties of the test substrate no longer representative of the entire substrate production lot. Although, the measurement of electrical properties may be carried out via non-contact and non-destructive techniques, the test substrates are discarded because their altered properties fail to ensure compliance with the customer""s specifications. This translates into a lower product yield and lost profits.
Equipped with, among others, the advantages of low temperature treatment associated with wet chemistry and dry processing associated with thermal oxidation, the present invention allows all substrates of a substrate production lot to undergo passivation under substantially similar processing conditions. The present invention provides a high quality oxide layer on all the substrate surfaces, which lend themselves to non-contact and reproducible measurement of the electrical properties of the underlying substrate layer. As a result, any one of the substrates of a substrate production lot may serve as the test substrate for measurement of the electrical properties of the underlying substrate layers. Furthermore, the substrates processed according to the present invention need not be discarded after the conclusion of non-contact or non-destructive measurements of the electrical properties because none of the substrates are subjected to high temperatures during surface passsivation according to the present invention. As a result, the need to use test substrates for monitoring production quality is totally eliminated.
In another aspect, the present invention provides a surface passivation apparatus. The apparatus includes: (1) a heating source for heating a substrate surface; (2) an ozone generator; and (3) a chamber for exposing a substrate surface to an oxidizing environment that includes a gas composition. The ozone generator of the present invention is configured to produce ozone within said chamber using said gas composition. Thus, the need for equipment necessary to transport ozone gas from a location off-site to the chamber where ozone gas is created to the chamber is obviated. It is important to keep in mind that all prior art designs that require ozone gas during surface passivation, have their ozone generator located outside the substrate processing chamber.
The heating source may include a single or plurality of infrared heating lamps such that each lamp operates at a power of and less than about 1000 watts, for example. Alternatively, in other embodiments, the lamp may operate at a power of about 1000 watts or higher. The ozone generator may be an ultraviolet (UV) frequency generating lamp, which is maintained ozone free when said UV frequency generating lamp produces ozone inside said chamber. A preferred embodiment of the surface passivation apparatus includes a UV transmitting layer that is disposed between the chamber and the ozone generator. The UV transmitting layer is at least substantially transparent to UV radiation and transmits at least a substantial portion of the UV radiation produced by the UV lamps. The chamber may be equipped with a gas inlet and a gas exhaust port such that substantially uniform flow of said gas composition is maintained inside said chamber.
These and other features of the present invention will be described in more detail below in the detailed description of the invention and in conjunction with the following figures.